The present invention generally relates to methods of designing semiconductor integrated circuits, and particularly to a method of diagnosing if a path delay of a semiconductor integrated circuit including a plurality of blocks can be converged within a target path delay before logic synthesis.
We have various techniques for countermeasure against defective delay paths in the design of semiconductor integrated circuits. For example, in the technique disclosed in JP-A-2888708, delay analysis is made after placement and routing, and if there is a defective delay path, cell displacement is made or circuit alteration is performed after turning back to logic design against the defective delay path. In another case of JP-A-2001-148425, delay analysis is made after cell placement but before routing, and cells are relocated against defective delay paths. Moreover in JP-A-11-282896, delay analysis is made after placement and routing, and the modification against the defective delay path is sorted into net list change, layout change or logic change according to the result of the analysis, then that sort of change being made against the defective delay path.
In other words, the above techniques analyze the net list after logic synthesis or the result of placement and routing and improve the delay according to the analysis against the defective delay path.